1. Field of the Invention
This invention relates to a semiconductor storage device, and more particularly to a control circuit for a read bus of a semiconductor storage device.
2. Description of the Related Art
In recent years, as the capacity of a semiconductor storage device increases, the chip size is inclined to increase. Consequently, the wiring for a read bus is so increasing that such problems as a delay in data transmission time and an increase in charge/discharge current of a wiring become significant.
Therefore, transmission of read data is frequently performed with a very small potential difference between two buss to achieve a high speed operation and reduction in current consumption.
FIG. 5 shows an example of a circuit construction of a semiconductor storage apparatus of the type described above.
Referring to FIG. 5, a read route is formed from a plurality of first read bus pairs RBUS1T and RBUS1N connected to a plurality of sense amplifiers 10, to which a bit line pair DT and DN is inputted, and inputted to a plurality of first data amplifiers 20, a second read bus pair RBUS2T and RBUS2N connected to the first data amplifiers 20 and also to a precharge circuit 30 and inputted to a second data amplifier 40, a third read bus pair RBUS3T and RBUS3N outputted from the second data amplifier and inputted to a data output buffer 50, and a still further bus from the data output buffer 50 to an output terminal DOUT.
Each of the sense amplifiers 10 is formed from a Please add the following claims: P-channel transistor T1 having a gate to which the bit line DT is inputted and connected between a power supply and the bit line DN, another P-channel transistor T2 having a gate to which the bit line DN is inputted and connected between the power supply and the bit line DT, an N-channel transistor T3 having a gate to which a plate selection signal PL is inputted and connected between the bit line DT and a nodal point ST, another N-channel transistor T4 having a gate to which the plate selection signal PL is inputted and connected between the bit line DN and another nodal point SN, a further N-channel transistor T5 having a gate to which the nodal point ST is inputted and connected to the ground GND and the nodal point SN, a still further N-channel transistor T6 having a gate to which the nodal point SN is inputted and connected between the ground GND and the nodal point ST, a pair of yet further N-channel transistors T7 and T8 connected in series between the first read bus RBUS1T and the ground GND, the N-channel transistor T7 having a gate to which a column selection line YSW is inputted, the N-channel transistor T8 having a gate to which the nodal point SN is inputted, and a pair of yet further N-channel transistors T9 and T10 connected in series between the first read bus RBUS1N and the ground GND, the N-channel transistor T9 having a gate to which the column selection line YSW is inputted, the N-channel transistor T10 having a gate to which the nodal point ST is inputted.
Each of the first data amplifiers 20 is formed from a P-channel transistor T11 having a gate to which a first data amplification activation signal DE1B is inputted and connected between the power supply and a nodal point A, another P-channel transistor T12 having a gate to which the first read bus RBUS1T is inputted and interposed between the nodal point A and the first read bus RBUS1N, a further P-channel transistor T13 having a gate to which the first read bus RBUS1N is inputted and interposed between the nodal point A and the first read bus RBUS1T, a pair of N-channel transistors T14 and T15 interposed in series between the second read bus RBUS2T and the ground GND, the N-channel transistor T14 having a gate to which a first read switch RSW1 is inputted, the N-channel transistor T15 having a gate to which the first read bus RBUS1N is inputted, a pair of further N-channel transistors T16 and T17 interposed in series between the second read bus RBUS2N and the ground GND, the N-channel transistor T16 having a gate to which the first read switch RSW1 is inputted, the N-channel transistor T17 having a gate to which the first read bus RBUS1T is inputted, a still further N-channel transistor T18 having a gate to which a first precharge signal PRE1 is inputted and connected between the first read bus RBUS1T and the power supply, and a yet further N-channel transistor T19 having a gate to which the first precharge signal PRE1 is inputted and connected between the first read bus RBUS1N and the power supply.
The precharge circuit 30 is formed from a P-channel transistor T20 having a gate to which a second precharge signal PRE2B is inputted and connected between the second read bus RBUS2T and the power supply, and another P-channel transistor T21 having a gate to which the second precharge signal PRE2B is inputted and connected between the second read bus RBUS2N and the power supply.
Further, the second data amplifier 40 is formed from an N-channel transistor T22 having a gate to which a second read switch RSW2 is inputted and connected between the second read bus RBUS2T and the third read bus RBUS3T, another N-channel transistor T23 having a gate to which the second read switch RSW2 is inputted and connected between the second read bus RBUS2N and the third read bus RBUS3N, a P-channel transistor T24 having a gate to which the third read bus RBUS3T is inputted and connected between the power supply and the third read bus RBUS3N, another P-channel transistor T25 having a gate to which the third read bus RBUS3N is inputted and connected between the power supply and the third read bus RBUS3T, a further N-channel transistor T26 having a gate to which the third read bus RBUS3T is inputted and connected between the third read bus RBUS3N and a nodal point B, a still further N-channel transistor T27 having a gate to which the third read bus RBUS3N is inputted and connected between the third read bus RBUS3T and the nodal point B, and a yet further N-channel transistor T28 having a gate to which a second data amplification activation signal DE2 is inputted and connected between the nodal point B and the ground GND.
It is to be noted that the transistors T1 and T2, the transistors T3 and T4, the transistors T5 and T6, the transistors T7 and T9, the transistors T8 and T10, the transistors T12 and T13, the transistors T14 and T16, the transistors T15 and T17, the transistors T18 and T19, the transistors T20 and T21, the transistors T22 and T23, the transistors T24 and T25, and the transistors T26 and T27 are transistors which individually exhibit same characteristics if an equal gate potential is applied.
Subsequently, operation of the semiconductor storage apparatus shown in FIG. 5 will be described. FIGS. 6(a) and 6(b) are waveform diagrams illustrating operation of the semiconductor storage apparatus shown in FIG. 5.
If a word line (not shown in FIG. 5) is selected and data of a memory cell (not shown in FIG. 5) appears on the bit line pair DT and DN, then if the plate selection signal PL is High, then the transistors T3 and T4 are conducting and the data is transmitted also to the nodal points ST and SN.
Thereafter, as seen also in FIGS. 6(a) and 6(b), if the column selection line YSW becomes High and the first data amplification activation signal DE1B becomes Low when the first precharge signal PRE1 is Low and the first read bus pair RBUS1T and RBUS1N is in a condition precharged to a potential lower by a threshold value of the transistors T18 and T19 than the power supply level, then a current route from the power supply to the ground GND via the transistors T11, T12, T9 and T10 and another current route from the power supply to the ground GND via the transistors T11, T13, T7 and T8 are produced.
In this instance, since the potentials at the nodal points ST and SN are different from each other, a difference is produced between the on-resistances (resistance values between the drain and the source) of the transistors T8 and T10, and a potential difference is produced also between the potentials of the first read buses RBUS1T and RBUS1N. Further, this potential difference is amplified by the first data amplifiers 20 and gradually becomes large.
FIGS. 6(a) and 6(b) illustrate a case of data when the DT, ST and RBUS1T sides become High and the DN, SN, RBUS1N sides become Low.
Then, if the first read switch RSW1 becomes High, then since the second precharge signal PRE2B is Low, a current route from the power supply to the ground GND via the transistors T20, T14 and T15 and another current route from the power supply to the ground GND via the transistors T21, T16 and T17 are produced. In this instance, since the potentials of the first read buses RBUS1T and RBUS1N are different from each other, a difference is produced between the on-resistances of the transistors T15 and T17, and a potential difference is produced also between the second read buses RBUS2T and RBUS2N.
Further, if the second read switch RSW2 becomes High , the n the potentials at the second read buses RBUS2T and RBUS2N are transmitted to the third read buses RBUS3T and RBUS3N via the transistors T22 and T23, respectively.
After the potentials are transmitted sufficiently to the third read buses RBUS3T and RBUS3N, if the second read switch RSW2 is changed to Low and the second data amplification activation signal DE2 is changed to High, then the potentials of the third read buses RBUS3T and RBUS3N are amplified to the power supply potential VCC and the potential ground GND, respectively, by the second data amplifier 40.
The data of the memory cell transmitted to the third read bus pair RBUS3T and RBUS3N as described above is outputted to the output terminal DOUT via the data output buffer 50.
FIG. 7 shows a relationship in arrangement of, from among the first data amplifiers 20 connected to the second read buses RBUS2T and RBUS2N in pair, the first data amplifier 20A connected to the second read buses RBUS2T and RBUS2N at a position proximate to connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N and the first data amplifier 20B connected to the second read buses RBUS2T and RBUS2N at a position remote from the connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N.
Referring to FIG. 7, the first data amplifier 20A receives a first data amplification activation signal DE1B(a), a first precharge signal PRE1(a), a first read switch RSW1(a) and a first read bus pair RBUS1T(a) and RBUS1N(a) as inputs thereto, and the sense amplifier 10A to which the first read bus pair RBUS1T(a) and RBUS1N(a) is connected receives a plate selection signal PL(a) and a bit line pair DT(a) and DN(a) as inputs thereto.
The first data amplifier 20B receives a first data amplification activation signal DE1B(b), a first precharge signal PRE1(b), a first read switch RSW1(b) and a first read bus pair RBUS1T(b) and RBUS1N(b) as inputs thereto, and the sense amplifier 10B to which the first read bus pair RBUS1T(b) and RBUS1N(b) is connected receives a plate selection signal PL(b) and a bit line pair DT(b) and DN(b) as inputs thereto.
It is to be noted that a precharge circuit 30, a second data amplifier 40 and a data output buffer 50 have constructions similar to those shown in FIG. 5, and the precharge circuit 30 is connected to the second read buses RBUS2T and RBUS2N at a position in the proximity of the connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N.
Here, parasitic resistances RT and RN of wirings are present between the points (RBUS2T(a) and RBUS2N(a)) of the second read bus pair RBUS2T and RBUS2N at which the first data amplifier 20A is connected thereto and the points (RBUS25(b) and RBUS2N(b)) of the second read bus pair RBUS2T and RBUS2N at which the first data amplifier 20B is connected thereto.
FIG. 8(a) illustrates variations of the potentials of the second read buses RBUS2T(a) and RBUS2N(a) and the second read buses RBUS2T(b) and RUBS2N(b) when the first data amplifier 20A is activated, and FIG. 8(b) illustrates variations of the potentials of the second read buses RBUS2T(a) and RBUS2N(a) and the second read buses RBUS2T(b) and RBUS2N(b) when the first data amplifier 20B is activated, for comparison.
The potentials Vt(a) and Vn(a) at which the second read bus pair RBUS2T(a) and RUBS2N(a) is saturated after the first read switch RSW1(a) becomes High and the potentials Vt(b) and Vn(b) at which the second read bus pair RBUS2T(a) and RBUS2N(a) is saturated after the first read switch RSW1(b) becomes High are given, where tile power supply voltage is represent by VCC, the on-resistances of the transistors T20 and T21 are represented by rP, the on-resistances of the transistors T14 and T15 and the transistors T16 and T17 connected in series are represented by rNh and eNl, respectively, and the magnitudes of the parasitic resistances RT and RN of the second read bus pair RBUS2T and RBUS2N are represented by rLINE, by the following expressions (1) to (4): ##EQU1##
The potential differences Vt(a)-Vn(a) and Vt(b)-Vn(b) of the second read bus pair RBUS2T(a) and RBUS2N(a) in the individual instances are given by the following expressions (5) and (6), respectively: ##EQU2##
Consequently, comparison between the potential differences Vt(a)-Vn(a) and Vt(b)-Vn(b) of the second read bus pair RBUS2T(a) and RBUS2N(a) in the individual cases is given by, since the parasitic resistance rLINE has a positive value, the following expression (7): EQU .vertline.Vt(a)-Vn(a).vertline.&gt;.vertline.Vt(b)-Vn(b).vertline.(7)
It is to be noted that, while the second read bus pair RBUS2T and RBUS2N is considered in terms of the saturation potential, since, even if comparison is made at a certain point of time before the second read bus pair RBUS2T and RBUS2N reaches the saturation potential, the expression (7) of a result of the comparison between the potential differences similarly applies, the potential difference between the second read bus pair RBUS2T(a) and RBUS2N(a) when the second read switch RSW2 is changed to High is larger and the operation margin of the second data amplifier 40 is larger when the first data amplifier 20A is activated than when the first data amplifier 20B is activated.
In this manner, in the conventional semiconductor storage device described above, since the potential difference of the second read bus pair RBUS2T(a) and RBUS2N(a) at the point at which they are inputted to the second data amplifier 40 is smaller when data is transmitted from the first data amplifier 20B which is connected to the second read buses RBUS2T and RBUS2N at a position remote from the connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N than when data is transmitted from the first data amplifier 20A which is connected to the second read buses RBUS2T and RBUS2N at a position near to the connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N, starting of amplification of the second data amplifier 40 must wait until the smaller potential difference is obtained sufficiently. Consequently, the conventional semiconductor storage device is disadvantageous in that such waiting causes a delay in data transmission time.
While the potential difference can be obtained in a shorter time if the capacities (current driving capacities) of the transistors T14, T16, T15 and T17 of the first data amplifiers 20 are raised with respect to that of the transistors T20 and T21 of the precharge circuit 30, this involves a limitation since this causes an increase in current consumption.
Further, if the second data amplifier 40 is set so as to start its amplification at a time at which the potential difference when data is transmitted from the first data amplifier 20B which is connected to the second read buses RBUS2T and RBUS2N at a position remote from the connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N is obtained sufficiently, then since transmission of data from the first data amplifier 20A which is connected to the second read buses RBUS2T and RBUS2N at a position near to the connection points between the second data amplifier 40 and the second read buses RBUS2T and RBUS2N will excessively lower the potentials of the second read bus pair RBUS2T and RBUS2N, a second problem is caused that the time for precharging the second read bus pair RBUS2T and RBUS2N again after the data is transmitted increases.
If the transistors T21 and T22 for precharging the second read buses RBUS2T and RBUS2N are made larger in order to reduce the precharging time, not only the current consumption increases, but also the capacities of the transistors T14, TiG, T15 and T17 become relatively low. Consequently, the preceding problem becomes more serious.
In recent years, since the capacity of semiconductor storage device has increased and also the chip area has increased, the parasitic resistances of the wirings for the second read bus pair RBUS2T and RBUS2N are high. Consequently, the problem described above has become significant.
Further, as the speed of operation of a semiconductor storage device increases, also another semiconductor storage device which has a pipeline function in the inside thereof and transfers data successively in a short cycle time has become available. In a semiconductor storage device of the type just mentioned, after the second read switch is switched off, unless the second read bus pair RBUS2T and RBUS2N is precharged at a high speed to prepare for data transmission of a next cycle, the cycle type characteristic is deteriorated. Consequently, also the second problem described above has become significant.